1. Field of the Invention
Embodiments of the invention relate to a shift register. In particular, embodiments of the invention relate to a shift register comprising an electrical fuse and a related method for operating the shift register.
This application claims priority to Korean Patent Application 10-2006-0077969, filed on Aug. 18, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
FIG. (FIG.) 1 illustrates a configuration of a conventional parallel register comprising electrical fuses. In particular, FIG. 1 illustrates four register D flip-flops 15, 16, 17, and 18, and electrical fuses 11, 12, 13, and 14 (each of which is also labeled “E-FUSE” in FIG. 1), which correspond to register D flip-flops 15, 16, 17, and 18, respectively. Although four D flip-flops and four corresponding electrical fuses are shown as an example in FIG. 1 for convenience of description, a conventional parallel circuit may comprise a greater number of D flip-flops and corresponding electrical fuses.
D flip-flops 15, 16, 17, and 18 receive input data D1, D2, D3, and D4, respectively, and then output the data to their respective output terminals Q1, Q2, Q3, and Q4 in response to a clock signal CLK. Each of D flip-flops 15, 16, 17, and 18 may further include a reset terminal rst for receiving a reset signal RESET. D flip-flops are well-known to those skilled in the art, so a detailed description thereof will be omitted here.
Input data signals Din1, Din2, Din3, and Din4 are applied to the input terminals of D flip-flops 15, 16, 17, and 18, respectively, and output through output terminals of D flip-flops 15, 16, 17 and 18, respectively, in response to a clock signal CLK. Electrical fuses 11, 12, 13, and 14 are selectively cut in accordance with input data signals Din1, Din2, Din3, and Din4 applied to and received from D flip-flops 15, 16, 17, and 18, respectively, and electrical fuses 11, 12, 13, and 14 generate final output signals QF1, QF2, QF3, and QF4, respectively.
It will be assumed that, for each of electrical fuses 11, 12, 13, and 14, when the electrical fuse receives a signal having a logic high level, the electrical fuse is cut and latches a signal having a logic high level. Thus, when input data signals D1, D2, D3, and D4 have a logic levels of low, low, low, and high, respectively, final output signals QF1, QF2, QF3, and QF4 are set to logic levels of low, low, low, and high, respectively.
However, the parallel register comprising electrical fuses shown in FIG. 1 needs an additional register (not shown) for the input data. That is, an additional register is needed to set input data signals D1, D2, D3, and D4 to have logic levels of, for example, low, low, low, and high, respectively. Although the disadvantage of requiring the additional register may not be very great if there are only four input data signals, as shown in FIG. 1, if many more input data signals are needed, it may be difficult to arrange all of the pads that may be needed for the input data signals, and the additional register may occupy a relatively large layout area.
Also, in addition to the parallel register comprising the electrical fuses, an additional parallel register used for a test mode is needed, so the parallel register may require an even larger layout area.
FIG. 2 illustrates a configuration of a conventional shift register comprising electrical fuses, wherein the shift register, unlike the parallel register of FIG. 1, does not require an additional parallel register for input data.
Referring to FIG. 2, the shift register of FIG. 2 comprises four register D flip-flops 25, 26, 27, and 28, and four corresponding electrical fuses 21, 22, 23, and 24. Each of electrical fuses 21, 22, 23, and 24 is also labeled “E-FUSE” in FIG. 2. As with the conventional parallel register of FIG. 1, although four D flip-flops and four corresponding electrical fuses are shown as an example in FIG. 2 for convenience of description, a conventional shift register may comprise a greater number of D flip-flops and corresponding electrical fuses.
D flip fops 25, 26, 27, and 28 receive data input through input terminals D1, D2, D3, and D4, respectively. In addition, D flip fops 25, 26, 27, and 28 output the received data through output terminals Q1, Q2, Q3, and Q4, respectively, in response to a clock signal CLK. D flip-flops 25, 26, 27, and 28 are connected to one another in series in such a way that a signal output by D flip-flop 25 is input to D flip-flop 26, a signal output by D flip-flop 26 is input to D flip-flop 27, and a signal output by D flip-flop 27 is input to D flip-flop 28. D flip-flops 25, 26, 27, and 28 receive input data (i.e., D flip-flop 25 initially receives input data signal Din) and then collectively shift the data in D flip-flops 25, 26, 27, and 28 in response to clock signal CLK. D flip-flops 25, 26, 27, and 28 may further include a reset terminal rst for receiving a reset signal RESET. D flip-flops are well-known to those skilled in the art, so a detailed description thereof will be omitted here.
Electrical fuse 21 is selectively cut in accordance with an output signal of D flip-flop 25, which corresponds to a signal (Din) previously input through input terminal D1 of D flip-flop 25. Likewise, electrical fuse 22 is selectively cut in accordance with an output signal of D flip-flop 26, which corresponds to a signal previously input through input terminal D2 of D flip-flop 26, electrical fuse 23 is selectively cut in accordance with an output signal of D flip-flop 27, which corresponds to a signal previously input through input terminal D3 of D flip-flop 27, and electrical fuse 24 is selectively cut in accordance with an output signal of D flip-flop 28, which corresponds to a signal previously input through input terminal D4 of D flip-flop 28. In addition, electrical fuses 21, 22, 23, and 24 output final output signals QF1, QF2, QF3, and QF4 during an operating cycle (i.e., a cycle of a clock signal CLK) during which the output signal of D flip-flop 28, which is applied to electrical fuse 24, has the first data value input through data signal Din.
It will be assumed that, for each of electrical fuses 21, 22, 23, and 24, when the electrical fuse receives a signal having a logic high level, the electrical fuse is cut and latches a signal having a logic high level. When, at relevant times of four sequential operating cycles corresponding to clock signal CLK (see FIG. 3), data input signal Din applied to an input terminal D1 of D flip-flop 25 has logic levels of high, low, low, and low, respectively, final output signals QF1, QF2, QF3, and QF4 of electrical fuses 21, 22, 23, and 24, respectively, will have logic levels of low, low, low, and high, respectively, during the fourth of those four sequential operating cycles.
Consequently, only electrical fuse 24 is cut (electrical fuses 21, 22, and 23 are not cut), so final output signals QF1, QF2, QF3, and QF4 are fixed having logic levels of low, low, low, and high, respectively. That is, a set of the final output signals of the shift register of FIG. 3 is fixed having logic levels of low, low, low, and high.
FIG. 3 is a timing diagram illustrating an operation of the shift register illustrated in FIG. 2. An exemplary operation of the shift register illustrated in FIG. 2 will now be described with reference to FIG. 3. After the first data value of input data signal Din (i.e., 1 in FIG. 3) input to D flip-flop 25 has been output by D flip-flop 28, electrical fuses 21, 22, 23, and 24 of FIG. 2 latch the data values 0 (i.e., a logic low level), 0, 0, and 1 (i.e., a logic high level), respectively. Thus, final output signals QF1, QF2, QF3, and QF4 have data values of 0, 0, 0, and 1, respectively, and final output signals QF1, QF2, QF3, and QF4 form a final output signal set for the shift register of FIG. 2.
A final output signal set for the shift register may be used for a mode register set (MRS), for example, or for another use.
A benefit of the shift register comprising electrical fuses described with reference to FIGS. 2 and 3 is that the shift register does not require an additional register in order to perform an operation that results in the electrical fuses outputting a final output signal set having, for example, logic levels of low, low, low, and high. However, to perform such an operation in the parallel register of FIG. 1, an additional register is needed in order to set input data signals Din1, Din2, Din3, and Din4 to logic levels of low, low, low, and high, respectively. However, in the shift register of FIG. 2, an error may occur in which an electrical fuse is cut during a operating cycle during which it was not supposed to be cut (i.e., during an unexpected operating cycle), which may produce an error in the final output signal set.
For example, referring to FIGS. 2 and 3, although a signal output by output terminal Q1 of D flip-flop 25 has a logic high level for only one operating cycle of clock signal CLK, the logic high level output by output terminal Q1 of D flip-flop 25 may affect electrical fuse 21, so electrical fuse 21 may be cut. A similar problem exists with respect to electrical fuses 22 and 23 of FIG. 2. Therefore, the shift register illustrated in FIG. 2 may not be reliable.
The conventional parallel register comprising electrical fuses has a relatively large layout area, and the conventional shift register comprising electrical fuses may output an erroneous final output signal set. Thus, an improved register solving both of the above problems is required.